`timescale 1us/1us
module fsm2_tb ();
   reg clk;
   reg reset;
   wire led;

   fsm2 fsm2(
    .clk(clk),
    .reset(reset),
    .led(led)
   ); 

    defparam fsm2.high1=25-1;
    defparam fsm2.low1=50-1;
    defparam fsm2.high2=75-1;
    defparam fsm2.low2=100-1;


   initial begin
            clk<=0;
            reset<=0;
    #10     reset<=1;
    #9000   $stop;
   end

   always #1 clk<=~clk;
endmodule
